The present invention generally relates to a clock producing apparatus for a PWM (pulse width modulation) system D/A converter for improving the S/N (signal to noise ratio) in a PWM system D/A converter.
Generally, although the apparatuses using digital art have been put into practical use for a long time, a D/A converter is used in the converting of analog values into discrete values so as to effect digital processing, and converting them again into analog values. Although a resistance ladder has been used in D/A converting systems, the IC adaptation is being effected to reduce the cost. But the conversion accuracy of the D/A converter cannot be provided in terms of accuracy of the resistance values which may be made in the IC interior, thus resulting in higher costs of the IC for higher accuracy. Recently, the conversion accuracy has been retained by a IC adapted D/A converter using a PWM system without depen-dence upon the resistance value accuracy within the IC.
Recently, three types of sampling frequency apparatuses (CD, DAT, BS tuner) have been put into practical use. The clocks of a certain multiple of the input sampling frequency become necessary for use as the clocks of the PWM system. The clock frequency of the PWM system must be switched in accordance with the sampling frequency of the input signals to be D/A converted. As shown in the spectrum chart of FIG. 3, the spectra of the unnecessary components in the frequency division within the switching circuit appear in the clock of the switching circuit output at this time. Thus, the S/N in the D/A converter of the PWM system may be deteriorated.
The state of the deterioration will be described hereinafter by the following simulation. The explanation is provided by a reference document "Japan Acoustics Society Lecture Theses Collection, October 1988, P411 (1-6-13 Consideration on Clock Jitters in the PWM type D/A Converter) by KANAAKI Tetsuhiko: Matsushita Electric Industrial Co., Ltd., AV Research Laboratory."
The above described reference literature states: "The clock jitters increase the noise level, and the noise level is proportional to the jitter amount". Namely, as shown in FIG. 3, the 1/n frequency division (n is an integer) of the clock fundamental wave for the PWM system D/A converter leaks with respect to the clock fundamental wave for the PWM system D/A converter so as to generate the clock jitters. In FIG. 3, one half frequency division is (n=2).
FIGS. 4(a)-4(b) show the waveform charts of a time region. FIG. 4(a) is a waveform chart of the clock fundamental wave only for a PWM system D/A converter. FIG. 4(b) is a waveform chart where the one half frequency division output has been mixed with the fundamental waves, showing the frequency region of FIG. 3 converted into the time region.
When the output is put through such an amplifier as shown in FIGS. 5(a)-5(c) (the amplifier A shown in FIG. 5(a) is an amplifier of a type where the feedback operation has been effected at the input, output operations into the inverter in the logic circuit, with the threshold level existing), such waveforms as in FIG. 5(b) and 5(c) are provided. FIG. 5(b) is a waveform chart in the logic circuit when such a fundamental waveform in FIG. 4(a) has been inputted into FIG. 5(a). FIG. 5(c) is a waveform chart in the logic circuit when the fundamental wave with the one half frequen-cy division output of the FIG. 4(b) being mixed in it has been inputted into FIG. 5(a). Therefore, it is found out that the jitters have been caused in FIG. 5(c). Therefore, the noise due to the jitters are increased as shown in the above described reference literature.
Assume that the sampling frequency is fs when the input sampling frequency has been changed, and the clocks of the PWM shaped D/A converter are given in fs X l (the l is an integer, 128, 192, 384, 768 are generally used under the existing state). But if the fs is changed into fs1 and fs2, the clocks of the D/A converter for PWM use are necessary to be changed into the fs1 . l and the fs2 . l. At this time, a selector circuit of the fs1 . l and fs2 . l becomes necessary.
FIG. 6 is a block diagram for explaining it. In FIG. 6, reference numeral 20 is a fsl X l oscillator, reference numeral 20 is a fs2 X l oscillator. The outputs thereof are inputted into the selector input terminals 22, 23 of the selector circuit 24, and the clock for the PWM system D/A converter to be outputted from the selector output terminal 25 is fed into the PWM system D/A converter 26. Also, the selector circuit 24 is switched by a switch-ing control signal to be inputted from the switching termi-nal 27 so as to select either of the selector input termi-nals 22 or 23.
FIG. 7 is a block diagram showing the details of the selector circuit 24. In FIG. 7, if the substrate voltage is slightly changed by the currents Ifs1 X l, Ifs2 X l running through the substrate when the fs1 X l oscillator 20, the fs2 X l oscillator 21 have been selected in a case where the impedance of the substrate resistor R is high, the spectrum corresponding to the frequency of the current running through the substrate resistor turns round into the selector circuit 24 and is registrated on the spectrum of the clock. Also, the turning round from the power supply voltage within the IC is also effected.
The unnecessary spectrum is registrated upon the clock spectrum of the PWM system in this manner so as to cause the deterioration of the S/N (signal to noise ratio) in the D/A converter of the PWM system.